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AS6C4008A rev. 1.12 512 k x 8 bit low power cmos sram alliance memory, inc. 551 taylor way, suite #1, san carlos, ca 94070 phone: 650 - 610 - 6800 0 revision history revision description issue date rev. 1. 12 initial issue may 15, 2012
AS6C4008A rev. 1.12 512 k x 8 bit low power cmos sram alliance memory, inc. 551 taylor way, suite #1, san carlos, ca 94070 phone: 650 - 610 - 6800 1 features ? fast access time : 55 ns ? low power consumption: operating current : 30 ma ( typ . ) standby current : 1 ? a ( typ . ) s l - version ? single 2. 7 v ~ 3.6v power supply ? all inputs and outputs ttl compatible ? fully static operation ? tr i - state output ? data retention voltage : 1.5v ( min .) ? g reen p ackage available ? package : 3 2 - pin 450 mil sop 32 - pin 8mm x 20mm t sop - i 32 - pin 8mm x 13.4 mm s t sop 36 - ball 6mm x 8mm tfbga general description the AS6C4008A is a 4,194,304 - bit low power cmos static random access memory organized as 524,288 words by 8 bits. it is fabricated using very high performance, high reliability cmos technology. its standby current is stable within the range of operating temperature. the AS6C4008A is well designed for very low power system application s , and particularly well suited for battery back - up nonvolatile memory application. the AS6C4008A operates from a single power supply of 2. 7 v ~ 3.6v and all inputs and outputs are fully ttl compatible 32 - pin 600 mil p - dip 32 - pin 400 mil tsop - ii product family product family operating temperature vcc range speed power dissipation standby( i sb1, typ.) operating( icc,typ.) AS6C4008A - 4 0 ~ 85 functional block diagram pin description symbol description a0 - a1 8 address inputs dq0 C cc power supply v ss ground nc no connection pin configuration decoder i / o data circuit control circuit 512 kx 8 memory array column i / o a 0 - a 18 vcc vss dq 0 - dq 7 ce # we # oe #
AS6C4008A rev. 1.12 512 k x 8 bit low power cmos sram alliance memory, inc. 551 taylor way, suite #1, san carlos, ca 94070 phone: 650 - 610 - 6800 2 a 1 2 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 d q 0 d q 1 d q 2 v s s a 1 4 v c c a 8 a 9 a 1 1 a 1 0 d q 7 d q 6 d q 5 d q 4 d q 3 a s 6 c 4 0 0 8 a s o p / p - d i p 2 8 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 1 7 1 6 1 5 2 0 1 9 1 8 2 2 2 3 2 4 2 5 2 6 2 7 2 1 a 1 3 c e # o e # w e # a 1 6 a 1 8 2 9 3 2 3 0 3 1 a 1 7 a 1 5 t s o p - i / s t s o p d q 3 a 1 1 a 9 a 8 a 1 3 d q 2 a 1 0 a 1 4 a 1 2 a 7 a 6 a 5 v c c d q 7 d q 6 d q 5 d q 4 v s s d q 1 d q 0 a 0 a 1 a 2 a 4 a 3 a s 6 c 4 0 0 8 a 2 8 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 1 7 1 6 1 5 2 0 1 9 1 8 2 2 2 3 2 4 2 5 2 6 2 7 2 1 o e # w e # c e # a 1 7 a 1 5 a 1 6 a 1 8 3 2 3 1 2 9 3 0 tfbga oe # we # a 12 a 11 a 13 nc a 18 a 10 a 14 a 15 dq 5 dq 6 dq 7 a 9 vss a 8 a 16 dq 4 vcc vcc dq 3 a 17 vss a 7 a 0 dq 2 dq 1 dq 0 a 6 a 1 a 3 a 5 nc a 4 a 2 1 2 3 4 5 6 h g c d e f a b ce # a s 6 c 4 0 0 8 a a 1 4 a 1 6 a 1 8 a 1 3 a 7 a 6 a 5 a 4 a 3 d q 3 d q 0 a 8 a 9 a 1 0 a 1 1 o e # c e # t s o p - i i 2 1 1 0 9 8 7 6 5 4 3 2 1 1 2 1 1 1 5 1 4 1 6 1 7 1 8 1 9 2 0 d q 1 a 1 2 a 1 a 0 v c c a 1 5 d q 6 a 2 d q 2 v s s d q 5 d q 7 2 5 2 2 2 3 2 4 3 2 2 9 3 0 3 1 2 6 2 7 2 8 d q 4 w e # a 1 7 1 3
AS6C4008A rev. 1.12 512 k x 8 bit low power cmos sram alliance memory, inc. 551 taylor way, suite #1, san carlos, ca 94070 phone: 650 - 610 - 6800 3 absolute maximun ratings * parameter symbol rating unit voltage on v cc relative to v ss v t 1 - 0.5 to 4.6 v voltage on any other pin relative to v ss v t 2 - 0.5 to v cc +0.5 v operating temperature t a - 4 0 to 85(i grade) stg - 65 to 150 d 1 w dc output current i out 50 ma *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect device reliab ility. truth table mode ce# oe# we# i/o operation supply current standby h x x high - z i sb ,i sb1 output disable l h h high - z i cc ,i cc1 read l l h d out i cc ,i cc1 write l x l d in i cc ,i cc1 note: h = v ih , l = v il , x = don't care.
AS6C4008A rev. 1.12 512 k x 8 bit low power cmos sram alliance memory, inc. 551 taylor way, suite #1, san carlos, ca 94070 phone: 650 - 610 - 6800 4 dc electrical characteristics parameter symbol test condition min. typ. * 4 max. unit supply voltage v cc 2.7 3.0 3.6 v input high voltage v ih *1 2. 2 - v cc +0. 3 v input low voltage v il *2 - 0. 2 - 0.6 v input leakage current i li v cc R in R ss - 1 - 1 a output leakage c urrent i lo v cc R out R ss , output disabled - 1 - 1 a output high voltage v oh i oh = - 1ma 2. 2 2.7 - v output low voltage v ol i ol = 2 ma - - 0.4 v average operating power supply current i cc cycle time = min. ce# = v il and i i/o = 0ma o ther pins at v il or v ih - 5 5 - 30 40 ma i cc1 cycle time = 1 s ce# Q i/o = 0ma o ther pins at 0.2v or v cc - 0.2v - 4 5 ma standby power supply current i sb ce# = v ih or ce2 = v il , o ther pins at v il or v ih - 0.3 1.25 m a i sb1 ce# R cc - 0.2v o ther s at 0.2v or v cc - 0.2v sli * 5 25 - 1 3 a 40 notes: 1. v ih (max) = v cc + 3.0 v for pulse width less than 10ns. 2. v il (min) = v ss - 3.0 v for pulse width less than 10ns. 3. over/undershoot specifications are characterized, not 100% tested. 4. typical values are included for reference only and are not guaranteed or tested. typical value s are measured at v cc = v cc (typ.) and t a = 25 5. this parameter is measured at v cc = 3.0v
AS6C4008A rev. 1.12 512 k x 8 bit low power cmos sram alliance memory, inc. 551 taylor way, suite #1, san carlos, ca 94070 phone: 650 - 610 - 6800 5 capacitance (t a = 25 parameter symbol min. max unit input capacitance c in - 6 pf input/output capacitance c i/o - 8 pf note : these parameters are guaranteed by device characterization, but not production tested. ac test conditions input pulse levels 0 .2 v to v cc - 0.2 v input rise and fall times 3 ns input and output timing reference levels 1.5v output load c l = 3 0pf + 1ttl , i oh /i ol = - 1ma/ 2 ma ac electrical characteristics (1) read cycle parameter sym . AS6C4008A - 55 unit min. max. read cycle time t rc 55 - ns address access time t aa - 55 ns chip enable access time t ace - 55 ns output enable access time t oe - 30 ns chip enable to output in low - z t clz * 10 - ns output enable to output in low - z t olz * 5 - ns chip disable to output in high - z t chz * - 20 ns output disable to output in high - z t ohz * - 20 ns output hold from address change t oh 10 - ns (2) write cycle parameter sym . AS6C4008A - 55 unit min. max. write cycle time t wc 55 - ns address valid to end of write t aw 50 - ns chip enable to end of write t cw 50 - ns address set - up time t as 0 - ns write pulse width t wp 45 - ns write recovery time t wr 0 - ns data to write time overlap t dw 25 - ns data hold from end of write time t dh 0 - ns output active from end of write t ow * 5 - ns write to output in high - z t whz * - 2 0 ns *these parameters are guaranteed by device characterization, but not production tested.
AS6C4008A rev. 1.12 512 k x 8 bit low power cmos sram alliance memory, inc. 551 taylor way, suite #1, san carlos, ca 94070 phone: 650 - 610 - 6800 6 t iming waveforms read cycle 1 (address controlled) (1,2) read cycle 2 ( ce# and oe# controlled) (1,3,4,5) notes : 1. we# is high for read cycle. 2.device is continuously selected oe# = low, ce# = low . 3.address must be valid prior to or coincident with ce# = low , ; otherwise t aa is the limiting parameter. 4.t clz , t olz , t chz and t ohz are specified with c l = 5pf. transition is measured 500mv from steady state. 5.at any given temperature and voltage condition, t chz is less than t clz , t ohz is less than t olz . dout data valid t oh t aa address t rc previous data valid dout data valid t oh oe # t ace ce # t aa address t rc high - z high - z t clz t olz t oe t chz t ohz
AS6C4008A rev. 1.12 512 k x 8 bit low power cmos sram alliance memory, inc. 551 taylor way, suite #1, san carlos, ca 94070 phone: 650 - 610 - 6800 7 write cycle 1 ( we# controlled) (1,2,3,5,6) write cycle 2 ( ce# c ontrolled) (1,2,5,6) notes : 1. we#, ce# must be high during all address transitions. 2.a write occurs during the overlap of a low ce# , low we# . 3.during a we# controlled write cycle with oe# low, t wp must be greater than t whz + t dw to allow the drivers to turn off and data to be placed on the bus. 4.during this period, i/o pins are in the output state, and input signals must not be applied. 5.if the ce# low transition occurs sim ultaneously with or after we# low transition, the outputs remain in a high impedance state. 6.t ow and t whz are specified with c l = 5pf. transition is measured 500mv from steady state. dout din data valid t d w t d h ( 4 ) high - z t whz we # t wp t cw ce # t wr t as t aw address t wc ( 4 ) t ow dout din data valid t d w t d h ( 4 ) high - z t whz we # t wp t cw ce # t wr t as t aw address t wc
AS6C4008A rev. 1.12 512 k x 8 bit low power cmos sram alliance memory, inc. 551 taylor way, suite #1, san carlos, ca 94070 phone: 650 - 610 - 6800 8 data retention characteristics parameter symbol test condition min. typ. max. unit v cc for data retention v dr ce# R v cc - 0.2v 1.5 - 3.6 v data retention current i dr v cc = 1.5 v ce# R v cc - 0.2v o ther pins at 0.2v or v cc - 0.2v sli 25 - 0.5 2.5 a 40 - 0.5 2.5 a sli - 0.5 10 a chip disable to data retention time t cdr see data retention waveforms (below) 0 - - ns recovery time t r t rc * - - ns t rc * = read cycle time data retention waveform v c c c e # v d r R Q i h t r t c d r v i h v c c ( m i n . )
AS6C4008A rev. 1.12 512 k x 8 bit low power cmos sram alliance memory, inc. 551 taylor way, suite #1, san carlos, ca 94070 phone: 650 - 610 - 6800 9 package outline dimension 32 pin 450 mil sop package outline dimension unit sym. inch.(base) mm(ref) a 0.1 20 (m ax ) 3.048 (m ax ) a1 0.004(min) 0.102(min) a2 0.11 6 (max) 2 . 946 (max) b 0. 01 6 ( typ ) 0.406 ( typ ) c 0.008(typ) 0.203(typ) d 0.817(max) 20.75(max) e 0.445 0.0 0 6 1 1.303 0.1 52 e1 0. 5 55 0.0 25 14 .0 97 0. 6 35 e 0.0 5 0(typ) 1.270 (typ) l 0. 0 3 3 0.0 17 0 . 8 38 0. 43 2 l 1 0.0 55 0.00 8 1 .3 97 0.2 03 s 0.026(max) 0 .660 (max) y 0.00 4(max) 0.101(max) 0 o - 10 o 0 o - 10 o
AS6C4008A rev. 1.12 512 k x 8 bit low power cmos sram alliance memory, inc. 551 taylor way, suite #1, san carlos, ca 94070 phone: 650 - 610 - 6800 10 32 pin 8mm x 20mm tsop - i package outline dimension unit sym. inch(base) mm(ref) a 0. 047 (max) 1.20 (max) a1 0.0 04 0.002 0.10 0.05 a2 0.0 39 0.00 2 1 . 00 0.0 5 b 0.00 9 0.00 2 0.2 2 0. 05 c 0.00 6 0.00 2 0.1 55 0.0 55 d 0 .724 0.00 8 18 .40 0. 2 0 e 0.315 0.00 8 8.00 0. 2 0 e 0.020 (typ) 0.50 (typ) hd 0.787 0.008 20.00 0.20 l 0. 0 24 0.00 4 0 . 6 0 0. 1 0 l1 0.0315 0.004 0.08 0.10 y 0.003 (max) 0.0 8 (max) 0 o 5 o 0 o 5 o
AS6C4008A rev. 1.12 512 k x 8 bit low power cmos sram alliance memory, inc. 551 taylor way, suite #1, san carlos, ca 94070 phone: 650 - 610 - 6800 11 32 pin 8 mm x 13.4mm stsop package outline dimension unit sym. inch(base) mm(ref) a 0. 049 (max) 1.25 (max) a1 0.0 0 4 0.002 0.10 0.05 a2 0.0 39 0.00 2 1 . 00 0.0 5 b 0.00 9 0.0 02 0.2 2 0.0 5 c 0.00 6 0.0 02 0.1 55 0.0 5 5 d 0 .465 0.00 8 11 . 8 0 0. 2 0 e 0.315 0.00 8 8.00 0. 2 0 e 0.020 (typ) 0.50 (typ) h d 0.528 0.00 8 13 .40 0. 20. l 0. 0 2 0.00 8 0 .50 0. 2 0 l1 0.031 0.00 5 0.8 0.1 25 y 0.003 (max) 0.076 (max) 0 o 5 o 0 o 5 o
AS6C4008A rev. 1.12 512 k x 8 bit low power cmos sram alliance memory, inc. 551 taylor way, suite #1, san carlos, ca 94070 phone: 650 - 610 - 6800 12 36 ball 6mm 8mm tfbga package outline dimension
AS6C4008A rev. 1.12 512 k x 8 bit low power cmos sram alliance memory, inc. 551 taylor way, suite #1, san carlos, ca 94070 phone: 650 - 610 - 6800 13 32 pin 600 mil p - dip package outline dimension note : d/e1/s dimension do not include mold flash. unit sym. inch(base) mm(ref) a1 0.0 15(min) 0. 381(min) a2 0. 155 0.00 5 3.937 0. 127 b 0.0 1 8 0.0 05 0. 457 0. 127 d 1.650 0.0 1 4 1 . 910 0. 254 e 0. 600 0.0 10 15.240 0. 254 e 1 0. 545 0.00 5 13.843 0. 1 27 e 0. 1 00(typ) 2.540 (typ) eb 0. 650 0.0 20 1 6.510 0. 508 . l 0. 1 58 0.0 43 4.013 1.092 s 0.0 75 0.0 10 1.905 0.254 q1 0.070 0.005 1.778 0.127
AS6C4008A rev. 1.12 512 k x 8 bit low power cmos sram alliance memory, inc. 551 taylor way, suite #1, san carlos, ca 94070 phone: 650 - 610 - 6800 14 32 - pin 400mil tsop -
AS6C4008A rev. 1.12 512 k x 8 bit low power cmos sram alliance memory, inc. 551 taylor way, suite #1, san carlos, ca 94070 phone: 650 - 610 - 6800 15 ordering information alliance organization vcc package operating temp speed ns AS6C4008A - 55pcn 512k x 8 3v 32pin 600mil dip commercial - 0c to 70c 55 AS6C4008A - 55sin 512k x 8 3v 32pin 450mil sop industrial - - 40c to 85c 55 AS6C4008A - 55tin 512k x 8 3v 32pin tsop 1 (8 x 20 mm) industrial - - 40c to 85c 55 AS6C4008A - 55stin 512k x 8 3v 32pin stsop (8 x 13.4 mm) industrial - - 40c to 85c 55 AS6C4008A - 55bin 512k x 8 3v 36pin tfbga (6mm x 8mm) industrial - - 40c to 85c 55 AS6C4008A - 55zin 512k x 8 3v 32pin 400mil tsop 11 industrial - - 40c to 85c 55 part numbering system as6c 4008 - 55 x x n low power sram prefix device number 40 = 4m 08 = by 8 access time package options: p = 32 pin 600 mil p - dip s = 32 pin 450 mil sop t = 32 pin tsop 1 (8mm x 20mm) z = 32 pin 400 mil tsop 11 st = 32 pin stsop (8mm x 13.4mm) b = 36 pin tfbga (6mm x 8mm) temperature range: c = commercial (0c to +70c) i = industrial ( - 40c to +85c) n = lead free rohs compliant part

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